1. Field of the Invention
Embodiments of the invention are generally related to fabrication of integrated circuit devices, and more specifically to routing of signals in an integrated circuit.
2. Description of the Related Art
Fabrication of integrated circuits generally involves depositing multiple layers of metal and insulation materials selectively on a silicon wafer. Particularly, the insulation (or dielectric) layers may be deposited between metal layers and may provide electrical insulation therebetween. The metal layers may connect one or more devices of the integrated circuit. In some cases, the metal layers may be interconnected to each other through vias etched in the intervening dielectric layers to route one or more signals of the integrated circuit.
The dielectric layers of an integrated circuit may vary in thickness as a result of various patterning processes that may be performed while forming the vias and patterned metal layers. Such thickness variations may be undesirable because they may reduce yield during fabrication of the integrated circuits and adversely affect performance of the integrated circuit.
In some cases, metal dummy fill structures may be provided in low metal density areas to produce a more flattened layout. The dummy fill structures may be formed as metal squares or metal rectangles that equalize spatial density of metal, thereby making the topology of metal layers more uniform and reducing the undesired variations in thicknesses of the dielectric layers. The metal dummy fill structures are generally formed in a final physical design step that is performed after a routing step which determines placement of signal lines that transfer signals in the integrated circuit.